SIR_CTRL=Val_0x0
Slave Interrupt Request Register
| SIR | Slave Interrupt Request When set, the I3C slave attempts to issue the SIR on the I^3C bus. Once issued and when the current master accepts (ACK) or if the I3C is unable to issue the SIR, then the I3C clears this bit automatically and updates the IBI_STS field. If the NACK response is received for the SIR, the controller reattempts the SIR upon detecting the next START condition from the master or after the bus available time. Once set, the application cannot clear this bit. |
| SIR_CTRL | Slave Interrupt Request Control 0 (Val_0x0): Send the assigned Dynamic address |
| MR | Master Request When set, the I3C attempts to issue the MR on the I^3C bus. Once issued and when the current master accepts or if the I3C is unable to issue the MR, then the I3C clears this bit automatically and updates the IBI_STS field. If NACK response is received for the MR, the I3C reattempts the MR upon detecting the next START condition from the master or after the bus available time. Once set, the application cannot clear this bit. |
| IBI_STS | IBI Completion Status This field is common for SIR and MR 1 (Val_0x1): IBI accepted by the master (ACK response received) 3 (Val_0x3): IBI not attempted |